Techniques for utilization of asymmetric secondary processing resources

ABSTRACT

A processor having asymmetric secondary processing resources. One disclosed embodiment includes a first execution resource to perform a first function and a second execution resource that also performs the second function, although the second processing resource is asymmetric to the first resource in that it has a lower throughput than the first processing resource. Switching logic switches execution from the first processing resource to the second processing resource in a reduced power consumption mode.

BACKGROUND

[0001] 1. Field

[0002] The present disclosure pertains to the field of processingsystems, and particularly the use of a secondary processing resource toexecute instructions under some conditions.

[0003] 2. Description of Related Art

[0004] Several techniques are presently used to control temperature andpower consumption of electronic components such as processors.Typically, maintaining a temperature of a component at an acceptablelevel is important to avoid damaging the component as well as to ensuresafety. On e way to control or reduce temperature is to limit powerconsumption. Additionally, with the popularity of mobile computing andcommunications devices, limiting power consumption to preserve batterylife is an increasingly important goal as well. Thus, power conservationmay be advantageous to limit heat generation, to preserve battery power,or both.

[0005] Dynamic clock disabling is one prior art technique to reducepower consumption. Dynamic clock disabling is the temporary orintermittent stopping of the clock or clocks of a processor. During theperiod in which the clock is stopped, clearly less power is consumed;however, no work can be performed if all of the clocks are stopped. Insome cases, a reduced level of functionality may be provided byperiodically stopping clocks; however, during “on” periods large andpower-hungry high performance logic structures are used. Anothervariation is to recognize when there is no work to be done, and to stopthe clocks at that point in time. Another variation is to stop clocks toa particular functional unit (e.g., a floating point unit) when thatunit is idle. However, when a unit or processor is idled, no work isaccomplished.

[0006] Dynamic frequency scaling is the change of processing frequency,typically effectuated by altering a clock frequency of the processor.While reduction of operating frequency decreases power proportionately,dynamic frequency scaling may in some cases require that a phase lockedloop re-acquire lock, which can be a relatively time consumingproposition. Moreover, dynamic frequency scaling also still keeps largepower-hungry structures active.

BRIEF DESCRIPTION OF THE FIGURES

[0007] The present invention is illustrated by way of example and notlimitation in the Figures of the accompanying drawings.

[0008]FIG. 1 illustrates one embodiment of a processor utilizing anasymmetric secondary processing resource.

[0009]FIG. 2 illustrates an embodiment of a processor having asymmetricsecondary pipeline segments.

[0010]FIG. 3 is a flow diagram illustrating a technique to reduce powerconsumption for one embodiment by utilizing duplicative but more powerefficient resources to perform processing.

[0011]FIG. 4 illustrates an embodiment with a decode segment of apipeline being split into two asymmetric execution resources.

[0012]FIG. 5 illustrates an embodiment in which the functionality of anentire processor core is replicated in an asymmetric fashion.

[0013]FIG. 6 illustrates an embodiment of a system that utilizes aprocessor having asymmetric secondary processing resources.

DETAILED DESCRIPTION

[0014] The following description discloses a processing system havingasymmetric secondary processing resources. In the following description,numerous specific details are set forth in order to provide a morethorough understanding of the present invention. It will be appreciated,however, by one skilled in the art that the invention may be practicedwithout such specific details. In other instances, control structuresand gate level circuits have not been shown in detail in order not toobscure the invention. Those of ordinary skill in the art, with theincluded descriptions, will be able to implement appropriate logiccircuits without undue experimentation.

[0015] Distribution of processing activity across asymmetric resourcesmay be advantageous in a number of ways. Some embodiments may allow newlow power but ‘awake’ modes that might not otherwise be possible. Someembodiments provide a secondary processing resource without the largearea increase associated with fully duplicating resources. Moreover,some embodiments can provide a processor that operates to reduce powerconsumption or reduce temperature without requiring other systemhardware or software changes, although hardware and/or software changesmay prove advantageous in some embodiments.

[0016] For example, in the embodiment of FIG. 1, a processor 100 maydistribute processing between a primary resource 110 and a secondaryresource 120. In the embodiment of FIG. 1, the primary resource 110 is arelatively large and performance-oriented resource, that performs thefunction ƒ(x) relatively rapidly, in a period of t1, and consuming apower p1. It is relatively expensive in terms of power consumption touse the primary resource 110 to perform the function ƒ(x), but ingeneral performance is desired. Moreover, the use of the primaryresource 110 to perform the function ƒ(x) typically generates more heat.

[0017] The secondary resource 120 also performs the function ƒ(x);however, the secondary resource is asymmetric with respect to theprimary resource in terms of its throughput, size, and powerconsumption. The secondary resource may be asymmetric with respect toany one or more of these characteristics, but they typically arecorrelated and all change together. Because the secondary resource neednot achieve as high of throughput as the primary resource 110, thesecondary resource 120 is typically smaller in size and consumes lesspower than the primary resource 110. Thus, as indicated in FIG. 1, thesecondary resource 120 performs the function ƒ(x) in a second amount oftime, t2, which is greater than t1, and using a second amount of powerp2, which is less than p1.

[0018] While the primary and secondary resources of FIG. 1 are at leastpartially functionally duplicative because they both perform thefunction ƒ(x), they need not be fully duplicative in functionality. Insome embodiments, the secondary resource 120 may implement only a subsetof the total functionality of the primary resource 110. In otherembodiments, however, the primary and secondary resources may be fullfunctional substitutes for one another, allowing equivalent operation,except for the time and power consumed.

[0019] The embodiment of FIG. 1 optionally also includes two sets ofshared resources 105 and 125. In some embodiments, post and/orpre-processing logic may be shared between primary and secondaryresources. Therefore shared resources may be used, but are not required.Additionally, the embodiment of FIG. 1 includes switching logic 130. Theswitching logic triggers a switch in processing resources. In oneembodiment, the switching logic 130 may move processing of the functionƒ(x) from exclusively being performed by the primary resource 110 toexclusively being performed by the secondary resource 120. In anotherembodiment, however, processing may be performed by the primary resource110 and the secondary resource 120 in a high throughput and/or highpower mode, and then scaled back to just one resource (e.g., first toexclusively the primary resource 110) and then to the lowest powerresource (e.g., secondly to only the secondary resource 120).

[0020] Various permutations of reduced power modes and processingresources may be used. For example, additional increments of processingresources may be provided between the highest and lowest powerresources, with different combinations of resources being active inorder to maintain some reasonable throughput on a reasonable powerbudget under the circumstances. For example, N different copies of aparticular functional unit or function may be provided, each having adifferent power consumption and a different throughput. A power awarescheduler may schedule instruction dispatch not only seeking to minimizethroughput, but also to stay within a certain total power consumption,or based on a current die temperature. Thus, various ones of the Nresources may be selected for execution of a particular function at aparticular time based on the power allotted or the current thermalenvironment.

[0021] In one embodiment, the processor 100 is a thermally awaremicroprocessor. The thermally aware microprocessor may scale back itspower consumption yet still continue processing at a steady pace byswitching to its lower throughput set of resources. In some embodiments,the processor switches to its lower throughput resources with littledisruption by draining instructions utilizing the high performance andhigh power resources, and then initiating execution using the secondaryresource. Such switching may be performed without stopping a clock orre-synchronizing a phase locked loop in some cases. Moreover, by usingsuch hardware mechanisms, the thermally aware microprocessor may achievepower conservation and/or cooling without external intervention andwithout any software support in some embodiments. Furthermore, withmultiple resources spreading out heat generation, less expensive heatdissipation technologies may be used to cool the processor 100 in somecases.

[0022] A prior art processor may be more prone to overheating since asingle set of resources may be continuously active. As a result of anoverheating event, a disruptive cooling period (e.g., stopping orreducing frequency of clocks) may be triggered according to prior arttechniques, causing the processor to operate very slowly and/or need tore-lock phase locked loops. Thus, an overheating period may degradeperformance significantly. In a thermally aware processor, the additionof secondary processing resources may consume a small amount ofprocessor area (e.g., area on a silicon die in some embodiments);however, the additional area may be performance justified by allowingthe processor to operate more coolly and avoid disruptive coolingperiods. For example, in one embodiment, five percent of die area may bededicated to providing functionally duplicative structures that allow alower yet continuous execution rate. Clocks may be gated to the largefunctionally duplicated structures, thereby eliminating the need tochange frequency and re-synchronize a phase locked loop. Thus, overallthe obtained energy to performance ratio may readily justify the expensein consumed die area in some cases.

[0023] Moreover, transistor reliability decreases and leakage currentincreases as temperature rises. These generally negative effects may bemitigated if lower processor temperatures are obtained by spreadingprocessing to the secondary processing resources to reduce heatconcentration. Since leakage current becomes a larger concern as devicegeometries shrink, keeping device temperature low should continue to bean important factor in reducing leakage current. Therefore, it may bedesirable to locate the functionally duplicative processing resourcesfar away from the resources which they are functionally duplicating tomaximize thermal de-coupling. The desire to thermally de-couple theseresources, however, typically will need to be tempered by the longsignal lines (and hence delay) that might be introduced in embodimentsin which the functionally duplicated resources interact substantiallywith a set of shared resources.

[0024] While a general purpose microprocessor may be one beneficiary ofthe use of asymmetric secondary resources to perform processing in somecases, other types of devices may benefit as well. For example, theprocessor 100 may be any type of processor such as a graphics processor,a network processor, a communications processor, a system-on-a-chipprocessor, an embedded processor, a digital signal processor or anyother known or otherwise available component which performs processing.Moreover, other electronic components that generate heat and are capableof operating at different throughput and power levels may likewisebenefit from using a secondary asymmetric resource at some times.

[0025] As a more specific example, FIG. 2 illustrates an embodiment of aprocessor 200 having asymmetric and at least partially functionallyduplicative primary and secondary pipeline segments. The primarystructure 210 includes wide superscalar pipelines with multiple-issuecapabilities. In particular, the primary structure 210 includes multipledecoders 212 and reservation station/re-order buffer pairs 214 capableof executing instructions in an out-of-order fashion. This structure isdesigned for performance, and therefore, its configuration is complex.On the contrary, the secondary structure 220 comprises a single decoder222 and a two entry first-in-first-out (FIFO) type instruction queue 224that feeds the execution units. The instruction queue 224 works like atwo entry reservation station/re-order buffer that issues instructionsin program order. Therefore the primary structure 210 includes a complexdecoder 212 pipeline segment and an out-of-order pipeline (OOP) segment,whereas the secondary structure includes a simple decoder 222 pipelinesegment and an in-order pipeline (IOP) segment.

[0026] In the embodiment of FIG. 2, the primary and secondary structurescooperate with shared resources to process instructions. A register file240 may be written to or read from by either the primary or thesecondary pipeline. Additionally, a set of execution units 225 may beused to execute the various instructions dispatched by the primary andsecondary pipelines. On the front end, a single fetch unit 205 may feedboth the primary and secondary pipelines. Finally, switching logic 230controls which pipeline is active.

[0027] Under normal operation (e.g., the die temperature is below agiven threshold), the wide superscalar pipelines provide theinstructions for the execution units, just like a typicalhigh-performance microprocessor. The Operating System (OS) may schedulesome “easy” tasks to the secondary pipeline as well in some embodiments.Once the temperature exceeds a selected threshold, or if the processoris switched to a low power mobile mode, the cooler secondary pipeline isused exclusively, and the primary pipeline is disabled (e.g., by clockgating).

[0028]FIG. 3 shows a transition process for the embodiment of FIG. 2. Inblock 300, whether the low power mobile mode is to be entered isdetermined. A user event may signify that the low power mode should beentered. For example, a user may close a lid of a laptop, press a buttonor hot key, or select a program or operating system option that causesentry into the low power mode. Similarly, whether a thresholdtemperature is exceeded is determined in block 310. If neither one ofthese conditions is true, then fetching of instructions to theout-of-order pipeline continues as indicated in block 305. Otherembodiments may test only one or the other of these conditions, or maytest other conditions, such as a composite power or temperaturemeasurement, etc.

[0029] If either one of these conditions is true (or if any condition istrue which justifies switching to only the in-order pipeline), then afetch stall is generated to stall fetching of instructions as indicatedin block 315. If instructions remain in the out-of-order pipeline (asdetermined in block 320), the instructions are executed and retired asindicated in block 330. The fetch unit may remain stalled until all theremaining instructions in the out-of-order pipeline are executed andretired. Once this process is completed, the fetch unit 205 isrestarted, and instructions are fetched to the in-order pipeline asindicated in block 325.

[0030] In some embodiments, the fetch unit 205 may also be a greatconsumer of power when operating at full speed. In one embodiment, thefetch unit 205 may be split into primary and secondary resources toalleviate the high power consumption issue by utilizing the secondaryresource at times. In another embodiment, the fetch unit 205 may beoperated in a low power mode when the overall low power mode thatdirects execution to the secondary pipeline is entered. For example, theclocks to the fetch unit 205 may be gated a portion of the time orperiodically.

[0031]FIG. 4 illustrates another embodiment that utilizes asymmetricsecondary resources. In this embodiment, a processor 400 has only asingle pipeline segment that is duplicated, the decoder. A primarystructure 410 includes a multiple instruction decoder 412, whereas asecondary and lower power structure 420 includes a single decoder 422.In this embodiment, a fetch unit 405 provides instructions to either (orboth of in some cases) the decoders 412 and 422. Both decoders 412 and422 feed decoded instructions into the out-of-order pipeline segment414, which passes instructions to a set of execution units 425. Again,switching logic 430 switches which decoder(s) are active at a giventime. In other embodiments, other pipeline segments than decoders mayalso be isolated and duplicated if those pipeline segments indeed proveto use large amounts of power. Moreover, execution units may be arrangedas duplicative primary and secondary resources. Execution units may beselected by throughput based on temperature or operating mode inaccordance with these general techniques.

[0032]FIG. 5 illustrates yet another embodiment in which the processingresource that is duplicated is a full processor core capable of runningan instruction set. In the embodiment of FIG. 5, a processor 500includes a main core 510 and a secondary core 520 which may beindependently used or used in concert as previously described undercontrol of switching logic 530. In this embodiment, the main core 510 isin a first power well 515 of an integrated circuit and is powered by afirst voltage supply as shown by a VCC1 supply being coupled to the maincore 510 on a VCC1 power supply line. The secondary core 520 is disposedin a second power well 525 and powered by a second power supply VCC2 ona VCC2 power supply line. In this embodiment, power may be removed froma power well when that core is not active. For example, in a low powerconsumption mode, the main core 510 may be disabled, and VCC1 may beremoved from the core. The secondary core may continue processinginstructions so that normal (albeit slower) function is maintained. Theuse of independent power wells may be particularly advantageous whereleakage current would otherwise be large, making an option of simplygating the clocks to the main core 510 less attractive. In otherembodiments, other primary and secondary resources previously discussedmay similarly be isolated in different power wells to obtain similaradvantages.

[0033] In some embodiments, both cores may be fully compatible (i.e.,fully decode and execute an entire instruction set). In otherembodiments, the secondary core 520 may only be capable of processing asubset of the entire instruction set. In such a case, a programmer orcompiler may be responsible for ensuring that tasks to be executed bythe secondary core 520 do not include unsupported instructions. In oneembodiment, the secondary core may not include support for instructionssuch as floating point or single instruction multiple data (SIMD)instructions. The switching logic 530 may detect such instructions andforce a switch back to the main core 510 if they occur. However, it maybe possible to run various minimal connectivity programs (e.g., email orother messaging programs) without using some complex orcompute-intensive instructions. In such cases, it may be advantageous tohave a core that executes only a subset of an instruction set and tocarefully architect routines to run on that core in a low powerconsumption mode.

[0034]FIG. 6 illustrates one embodiment of a system utilizing aprocessor having asymmetric secondary resources. In the embodiment ofFIG. 6, the processor 200 from FIG. 2 is shown; however, otherembodiments as discussed may be used in this or other systemarrangements. In the embodiment of FIG. 6, a memory controller 690 iscoupled to the processor 200, and a main memory 695 is coupled to thememory controller 690 by a bus 692. Also included in the system are acommunication and/or network interface 650, and a message indicator 655.The message indicator and the communications and/or network interface650 are coupled to the processor such that programs executed by theprocessor can utilize these devices. Many different systemconfigurations are possible, and the particular configuration used isnot particularly important. Moreover, various components in the systemmay be integrated together, rearranged, coupled together in differentways, etc.

[0035] In one embodiment, the main memory 695 of FIG. 6 includes ascheduling routine 610 such as a scheduler in an operating system. Thescheduling routine 610 is aware that the processor 200 includes asecondary resource (i.e., secondary structure 220). Therefore, thescheduling routine 610 selects tasks to execute on the secondarypipeline. In some cases, relatively simple and/or latency-insensitivetasks are selected.

[0036] In one embodiment, the main memory 695 of FIG. 6 includes amessaging program 620. The messaging program 620 may be an emailprogram, an instant messenger program, a pager program, a phone callprogram, or any messaging program. In some cases, it is desirable toallow the system to enter a very low power mode in which the system isnot being used by the user, however, the user wishes to be alerted if amessage is received. In this case, the primary resources (e.g., theout-of-order pipeline) may be shut down, and the in-order-pipeline maybe used to continue to monitor the communication/networking interface650 according to the messaging program 620. If a message is received,the processor may generate a message indication via the messageindicator 655. The message indicator 655 may be anything from an audiodevice that generates an audible sound, to a light emitting diode thatlights up or changes flashing frequency, etc., to a display that changesin response to the message being received.

[0037] A typical hardware design may go through various stages, fromcreation to simulation to fabrication. Data representing a design mayrepresent the design in a number of manners. First, as is useful insimulations, the hardware may be represented using a hardwaredescription language or another functional description languageAdditionally, a circuit level model with logic and/or transistor gatesmay be produced at some stages of the design process. Furthermore, mostdesigns, at some stage, reach a level of data representing the physicalplacement of various devices in the hardware model. In the case whereconventional semiconductor fabrication techniques are used, the datarepresenting the hardware model may be the data specifying the presenceor absence of various features on different mask layers for masks usedto produce the integrated circuit. In any representation of the design,the data may be stored in any form of a machine readable medium. In asoftware design, the design typically remains on a machine readablemedium. An optical or electrical wave modulated or otherwise generatedto transmit such information, a memory, or a magnetic or optical storagesuch as a disc may be the machine readable medium. Any of these mediumsmay “carry” the design information. A processing device utilizingdisclosed techniques may be represented in these or other manners andaccordingly may be carried in various media.

[0038] Thus, a processing system having asymmetric secondary processingresources is disclosed. While certain exemplary embodiments have beendescribed and shown in the accompanying drawings, it is to be understoodthat such embodiments are merely illustrative of and not restrictive onthe broad invention, and that this invention not be limited to thespecific constructions and arrangements shown and described, sincevarious other modifications may occur to those ordinarily skilled in theart upon studying this disclosure.

What is claimed is:
 1. An apparatus comprising: a first processingresource to perform a first function; a second processing resource toalso perform said first function, said second processing resource beingasymmetric in throughput with respect to said first processing resource;switching logic to switch execution from said first processing resourcein a first mode to said second processing resource in an reduced powerconsumption mode.
 2. The apparatus of claim 1 wherein said switchinglogic is to switch execution to said second processing resource inresponse to a temperature level of said apparatus reaching a selectedlevel.
 3. The apparatus of claim 1 wherein said switching logic is toswitch execution to said second processing resource in response to auser event causing entry into said reduced power consumption mode. 4.The apparatus of claim 1 further comprising: shared resources with whichthe second processing resource interacts in the reduced powerconsumption mode and with which the first processing resource interactsin the first mode.
 5. The apparatus of claim 1 wherein said firstprocessing resource comprises a first decoder and wherein said secondprocessing resource comprises a second decoder and wherein said firstdecoder and said second decoder can both decode a full instruction set.6. The apparatus of claim 1 wherein said first processing resourcecomprises an out-of-order pipeline segment and wherein said secondprocessing resource comprises an in-order pipeline segment.
 7. Theapparatus of claim 6 wherein said first processing resource furthercomprises a multiple instruction decoder and wherein said secondprocessing resource further comprises a single instruction decoder. 8.The apparatus of claim 7 further comprising a shared fetch unit.
 9. Theapparatus of claim 1 wherein said first processing resource comprises afirst processor core, and wherein said second processing resourcecomprises a second processor core, and further wherein said second corehas inferior processing throughput with respect to said first core. 10.The apparatus of claim 9 wherein said second core has a separate powersupply from said first core.
 11. The apparatus of claim 10 wherein poweris removed from said first processing core in said reduced powerconsumption mode.
 12. The apparatus of claim 1 wherein said firstprocessing resource and said second processing resources are powered viadifferent power supplies lines, and further wherein said switch logic isto shut off power to said first processing resource in said reducedpower consumption mode.
 13. An apparatus comprising: a first processorpipeline segment; a second processor pipeline segment, said secondprocessor pipeline segment being a simple processor pipeline segmentrelative to said first processor pipeline segment; pipeline switch logicto switch execution from said first processor pipeline segment in afirst mode to said second processor pipeline segment in a low powerconsumption mode.
 14. The apparatus of claim 13 wherein said firstprocessor pipeline segment comprises an out-of-order pipeline segmentand wherein said second processor pipeline segment comprises an in-orderpipeline segment.
 15. The apparatus of claim 14 further comprising: afetch mechanism to fetch instructions for both said first processorpipeline segment and said second processor pipeline segment.
 16. Theapparatus of claim 15 wherein said fetch mechanism comprises an adaptivefetch mechanism to operate in a reduced power consumption fetching modewhen said apparatus is in said low power consumption mode.
 17. Theapparatus of claim 16 wherein said fetch mechanism is clock gated insaid reduced power consumption fetching mode.
 18. The apparatus of claim16 further comprising: a primary decoder to decode instructions for saidfirst processor pipeline segment; a secondary decoder to decodeinstructions for said second processor pipeline segment.
 19. Theapparatus of claim 16 further comprising: a register file accessible byboth said first processor pipeline segment and said second processorpipeline segment; a plurality of execution units shared by said firstprocessor pipeline segment and said second processor pipeline segment.20. The apparatus of claim 19 wherein said second processor pipelinesegment further comprises: a first-in-first-out instruction queue. 21.The apparatus of claim 16 wherein said pipeline switch logic is toswitch from only execution in said first processor pipeline segment insaid first mode to only execution in said second processor pipelinesegment in said low power consumption mode.
 22. The apparatus of claim16 wherein said pipeline switch logic is switch from execution in saidfirst processor pipeline segment and optionally said second processorpipeline segment in said first mode to only execution in said secondprocessor pipeline segment in said low power consumption mode.
 23. Theapparatus of claim 14 wherein said pipeline switch logic is to switch tosaid low power consumption mode in response to a temperature indicatorfor said apparatus reaching a selected level.
 24. The apparatus of claim14 wherein said pipeline switch logic is to switch to a limitedresponsiveness state in response to a user generated event.
 25. Theapparatus of claim 24 wherein in said limited responsiveness state, saidapparatus is to detect incoming messages from a communicationsinterface.
 26. The apparatus of claim 13 wherein said secondaryprocessor pipeline segment is an isolated pipeline segment having aseparate power supply from said first processor pipeline segment. 27.The apparatus of claim 26 wherein said secondary processor pipelinesegment comprises an in-order processor pipeline segment.
 28. Theapparatus of claim 13 wherein said pipeline switch logic is to execute aplurality of in progress instructions in said first processor pipelinesegment until said plurality of in progress instructions retire and thento switch to said second processor pipeline segment when transitioningto said low power consumption mode.
 29. A method comprising: executinginstructions via a first execution resource in a first mode;transitioning to a low power mode; executing instructions via a secondexecution resource in the low power mode.
 30. The method of claim 29wherein said first execution resource is a first pipeline segment andwherein said second execution resource is a second pipeline segment. 31.The method of claim 30 wherein said second pipeline segment is a reducedcomplexity pipeline segment with respect to said first pipeline segment.32. The method of claim 31 wherein said second pipeline segment is anin-order pipeline segment and said first pipeline segment is anout-of-order pipeline segment.
 33. The method of claim 30 furthercomprising: fetching instructions for both pipeline segments via a fetchunit; reducing power consumption of said fetch unit in said low powermode.
 34. The method of claim 33 further comprising: decodinginstructions for said first pipeline segment with a complex decoder;decoding instructions for said second pipeline segment with a simpledecoder relative to said complex decoder.
 35. The method of claim 30wherein transitioning comprises: retiring a plurality of in-progressinstructions.
 36. The method of claim 30 further comprises: sharing aplurality of registers and execution units between said first pipelineand said second pipeline.
 37. The method of claim 29 further comprising:removing a power supply from said first execution resource whenoperating in said low power mode.
 38. The method of claim 37 whereinsaid first execution resource is a first execution core having a firstpower supply line and wherein said second execution resource is a secondexecution resource having a second power supply line.
 39. A systemcomprising: a memory to store a plurality of instructions; a processorto execute said plurality of instructions using either a first set ofresources or a second asymmetric set of resources, said processor toproduce a same result using either said first set of resources or saidsecond set of resources, said processor to use said first set ofresources in a first mode and to use said second set of resources in asecond mode.
 40. The system of claim 39 further comprising: a networkinterface, wherein in said second mode said second processing resourceexecutes a network monitoring routine to maintain connectivity via saidnetwork interface.
 41. The system of claim 40 wherein said networkmonitoring routine is to generate a message indicator when a new messageis detected.
 42. The system of claim 39 further comprising a thermalsensor, wherein said processor is to enter said second mode in responseto said thermal sensor indicating a threshold temperature.
 43. Thesystem of claim 41 wherein said processor is to enter said second modein response to a user generated event.
 44. A processor comprising: anin-order pipeline; an out-of-order-pipeline; a plurality of registersaccessible by both the in-order pipeline and said out-of-order pipeline;a plurality of execution units operative in response to instructionsprocessed by said in-order pipeline and said out-of-order pipeline. 45.The processor of claim 4 further comprising: a complex decoder to decodeinstructions for said out-of-order pipeline; a simple decoder to decodeinstructions for said in-order pipeline.
 46. The processor of claim 45further comprising: a fetch unit to fetch in a first mode for saidin-order pipeline and to fetch in a second mode for said out-of-orderpipeline.
 47. The processor of claim 44 wherein said out-of-orderpipeline is to be disabled in a low power consumption mode.
 48. Theprocessor of claim 44 wherein said low power consumption mode is to beentered in response to a high temperature.
 49. The processor of claim 47wherein said low power consumption mode is a messaging connect mode. 50.An apparatus comprising: first means for performing a first processingfunction; second means for performing said first processing function;means for switching between use of said first processing function andsaid second processing function.
 51. The apparatus of claim 50 whereineach of said first processing means and said second processing means isan execution core.